mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 106

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Programmable Timer
8.4.5 Timer Counter Register
8.4.6 Timer Control 1 Register
Data Sheet
106
The 16-bit read-only timer count register (TCNT) contains the prescaled value of
the 16-bit timer. A full counter read addresses the most significant byte (MSB) first.
A read of this address causes the least significant byte (LSB) to be latched into a
buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state
of the counter at the time of the MSB read cycle.
In normal modes, TCNT is read-only.
The bits of the timer control 1 register (TCTL1) specify the action taken as a result
of a successful OCx compare.
OM2–OM5 — Output Mode Bits
OL2–OL5 — Output Level Bits
Address: $000E — TCNT High
Address: $000F — TCNT Low
Address:
These control bit pairs are encoded to specify the action taken after a successful
OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear.
Refer to
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
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For More Information On This Product,
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Bit 15
Bit 15
OM2
Table 8-3
Bit 7
Bit 7
Bit 7
0
0
0
Figure 8-11. Timer Control 1 Register (TCTL1)
Figure 8-10. Timer Counter Registers (TCNT)
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= Unimplemented
Bit 14
Bit 6
OL2
Programmable Timer
14
0
6
0
6
0
for the coding.
Bit 13
OM3
Bit 5
13
0
5
0
5
0
Bit 12
Bit 4
OL3
12
4
4
0
0
0
Bit 11
OM4
Bit 3
11
0
3
0
3
0
Bit 10
Bit 2
OL4
10
0
2
0
2
0
MC68HC711D3 — Rev. 2
OM5
Bit 9
Bit 1
9
0
1
0
1
0
MOTOROLA
Bit 08
Bit 8
Bit 0
Bit 0
Bit 0
OL5
0
0
0