mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 65

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.4 Low-Power Operation
4.4.1 Stop Mode
MC68HC711D3 — Rev. 2
MOTOROLA
The M68HC11 Family of microcontroller units (MCU) has two programmable low
power-consumption modes: stop and wait. In the wait mode, the on-chip oscillator
remains active. In the stop mode, the oscillator is stopped. This subsection
describes these two low power-consumption modes.
The STOP instruction places the MCU in its lowest power-consumption mode,
provided the S bit in the CCR is cleared. In this mode, all clocks are stopped,
thereby halting all internal processing.
To exit the stop mode, a low level must be applied to either the IRQ, XIRQ, or
RESET pin. An external interrupt used at IRQ is only effective if the I bit in the CCR
is cleared. An external interrupt applied at the XIRQ input is effective, regardless
of the setting of the X bit of the CCR. However, the actual recovery sequence
differs, depending on the X bit setting. If the X bit is cleared, the MCU starts with
the stacking sequence leading to the normal service of the XIRQ request. If the X
bit is set, the processing always continues with the instruction immediately
following the STOP instruction. A low input to the RESET pin always results in an
exit from the stop mode, and the start of MCU operations is determined by the reset
vector.
The CPU will not exit stop mode correctly when interrupted by IRQ or XIRQ if the
instruction preceding STOP is a column 4 or 5 accumulator inherent (opcodes $4X
and $5X) instruction, such as NEGA, NEGB, COMA, COMB, etc. These
single-byte, two-cycle instructions must be followed by an NOP, then the STOP
command. If reset is used to exit stop mode, the CPU will respond properly.
A restart delay is required if the internal oscillator is being used. The delay allows
the oscillator to stabilize when exiting the stop mode. If a stable external oscillator
is being used, the delay (DLY) bit in the OPTION register can be cleared to bypass
the delay. If the DLY bit is clear, the RESET pin would not normally be used to exit
the stop mode. The reset sequence sets the DLY bit, and the restart delay would
be reimposed.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-4. Highest Priority Interrupt Selection (Continued)
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Resets, Interrupts, and Low-Power Modes
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Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer input capture 4/output compare 5
Resets, Interrupts, and Low-Power Modes
Low-Power Operation
Data Sheet
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