mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 116

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Programmable Timer
Data Sheet
116
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag
Address:
Address:
not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow
interrupts are inhibited, and the system operates in a polled mode, which
requires PAOVF to be polled by user software to determine when an overflow
has occurred. When the PAOVI control bit is set, a hardware interrupt request
is generated each time PAOVF is set. Before leaving the interrupt service
routine, software must clear PAOVF by writing to the TFLG2 register.
The PAIF status bit is automatically set each time a selected edge is detected
at the PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with
a 1 in the corresponding data bit position (bit 4). The PAII control bit allows
configuring the pulse accumulator input edge detect for polled or
interrupt-driven operation but does not affect setting or clearing the PAIF bit.
When PAII is 0, pulse accumulator input interrupts are inhibited, and the system
operates in a polled mode. In this mode, the PAIF bit must be polled by user
software to determine when an edge has occurred. When the PAII control bit is
set, a hardware interrupt request is generated each time PAIF is set. Before
leaving the interrupt service routine, software must clear PAIF by writing to the
TFLG register.
Reset:
Reset:
Read:
Write:
Read:
Write:
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Bit 7
Bit 7
TOF
TOI
Figure 8-22. Timer Interrupt Mask 2 Register (TMSK2)
0
0
Figure 8-23. Timer Interrupt Flag 2 Register (TFLG2)
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RTIF
RTII
Programmable Timer
6
0
6
0
PAOVF
PAOVI
5
0
5
0
PAIF
PAII
4
4
0
0
3
0
0
3
0
0
2
0
0
2
0
0
MC68HC711D3 — Rev. 2
PR1
1
0
1
0
0
MOTOROLA
Bit 0
Bit 0
PR0
0
0
0