mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 39

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

3.2.5 Program Counter (PC)
3.2.6 Condition Code Register (CCR)
3.2.6.1 Carry/Borrow (C)
3.2.6.2 Overflow (V)
3.2.6.3 Zero (Z)
MC68HC711D3 — Rev. 2
MOTOROLA
The program counter, a 16-bit register, contains the address of the next instruction
to be executed. After reset, the program counter is initialized from one of six
possible vectors, depending on operating mode and the cause of reset.
See
This 8-bit register contains:
In the M68HC11 CPU, condition codes are updated automatically by most
instructions. For example, load accumulator A (LDAA) and store accumulator A
(STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to
what condition codes are affected by a particular instruction.
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during
an arithmetic operation. The C bit also acts as an error flag for multiply and divide
operations. Shift and rotate instructions operate with and through the carry bit to
facilitate multiple-word shift operations.
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the
V bit is cleared.
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation
is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied
subtraction and the condition codes, including Z, reflect the results of that
subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no
other condition flags. For these operations, only = and
determined.
Test or boot
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Table
Normal
Mode
Freescale Semiconductor, Inc.
Five condition code indicators (C, V, Z, N, and H)
Two interrupt masking bits (IRQ and XIRQ)
One stop disable bit (S)
For More Information On This Product,
3-1.
Go to: www.freescale.com
Central Processor Unit (CPU)
POR or RESET Pin
Table 3-1. Reset Vector Comparison
$BFFE, $BFFF
$FFFE, $FFFF
Clock Monitor
$FFFC, $FFFD
$BFFC, $FFFD
Central Processor Unit (CPU)
Table
conditions can be
3-2, which shows
COP Watchdog
$FFFA, $FFFB
$BFFA, $FFFB
CPU Registers
Data Sheet
39