mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 92

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI)
7.7 SPI Registers
7.7.1 SPI Control Register
Data Sheet
92
transfer begins when the SCK line goes to its active level, which is the edge at the
beginning of the first SCK cycle. The transfer ends in a slave in which CPHA equals
one when SPIF is set. For a slave, after a byte transfer, SCK must be in inactive
state for at least 2 E-clock cycles before the next byte transfer begins.
The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and
data storage functions. This sub-section provides a description of how these
registers are organized.
SPIE — Serial Peripheral Interrupt Enable Bit
SPE — Serial Peripheral System Enable Bit
DWOM — Port D Wired-OR Mode Bit
MSTR — Master Mode Select Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
Address:
DWOM affects all six port D pins.
When the clock polarity bit is cleared and data is not being transferred, the SCK
pin of the master device has a steady state low value. When CPOL is set, SCK
idles high. Refer to
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data
relationship between master and slave. The CPHA bit selects one of two
different clocking protocols. Refer to
Polarity
Reset:
Read:
Write:
0 = SPI interrupt disabled
1 = SPI interrupt enabled
0 = SPI off
1 = SPI on
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
Freescale Semiconductor, Inc.
For More Information On This Product,
U = Unaffected
$0028
SPIE
Bit 7
Controls.
0
Serial Peripheral Interface (SPI)
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Figure 7-3. SPI Control Register (SPCR)
SPE
6
0
Figure 7-2
DWOM
5
0
and
MSTR
7.4 Clock Phase and Polarity
4
0
Figure 7-2
CPOL
3
0
and
7.4 Clock Phase and
CPHA
2
1
MC68HC711D3 — Rev. 2
SPR1
U
1
Controls.
MOTOROLA
SPR0
Bit 0
U