mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 42

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Central Processor Unit (CPU)
3.5.1 Immediate
3.5.2 Direct
3.5.3 Extended
3.5.4 Indexed
3.5.5 Inherent
Data Sheet
42
which the argument is fetched or stored or the address from which execution is to
proceed. The effective address can be specified within an instruction, or it can be
calculated.
In the immediate addressing mode, an argument is contained in the byte(s)
immediately following the opcode. The number of bytes following the opcode
matches the size of the register or memory location being operated on. There are
2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective
address is the address of the byte following the instruction.
In the direct addressing mode, the low-order byte of the operand address is
contained in a single byte following the opcode, and the high-order byte of the
address is assumed to be $00. Addresses $00–$FF are thus accessed directly,
using 2-byte instructions. Execution time is reduced by eliminating the additional
memory access required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the
memory map can be configured for combinations of internal registers, RAM, or
external memory to occupy these addresses.
In the extended addressing mode, the effective address of the argument is
contained in two bytes following the opcode byte. These are 3-byte instructions (or
4-byte instructions if a prebyte is required). One or two bytes are needed for the
opcode and two for the effective address.
In the indexed addressing mode, an 8-bit unsigned offset contained in the
instruction is added to the value contained in an index register (IX or IY). The sum
is the effective address. This addressing mode allows referencing any memory
location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether a prebyte is required.
In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. Operations that use only the index registers
or accumulators, as well as control instructions with no arguments, are included in
this addressing mode. These are 1- or 2-byte instructions.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Central Processor Unit (CPU)
MC68HC711D3 — Rev. 2
MOTOROLA