mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 82

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface (SCI)
Data Sheet
82
SCR2–SCR0 — SCI Baud Rate Select Bits
These three bits select receiver and transmitter bit rate based on output from
baud rate prescaler stage.
The prescale bits, SCP1 and SCP0, determine the highest baud rate and
the SCR2–SCR0 bits select an additional binary submultiple ( 1
through 128) of this highest baud rate. The result of these two dividers in series
is the 16 X receiver baud rate clock. The SCR2–SCR0 bits are not affected by
reset and can be changed at any time, although they should not be changed
when any SCI transfer is in progress.
Figure 6-8
determine the highest baud rate. The rate select bits determine additional divide
by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock
is the result of dividing the RT clock by 16.
Freescale Semiconductor, Inc.
SCR2–SCR0
For More Information On This Product,
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Serial Communications Interface (SCI)
illustrates the SCI baud rate timing chain. The prescale select bits
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Prescaler
Divide
Table 6-2. Baud Rate Selects
128
By
16
32
64
1
2
4
8
4800
4800
2400
1200
600
300
150
—
—
(Prescaler Output from
Highest Baud Rate
9600
9600
4800
2400
1200
600
300
150
—
MC68HC711D3 — Rev. 2
Table
2, 4
38.4 K
38.4 K
19.2 K
6-1)
9600
4800
2400
1200
MOTOROLA
600
300