mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 107

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mc68hc11d0cfn2

Manufacturer Part Number
mc68hc11d0cfn2
Description
M68hc11 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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8.4.7 Timer Interrupt Mask 1 Register
MC68HC711D3 — Rev. 2
MOTOROLA
NOTE:
The timer interrupt mask 1 register (TMSK1) is an 8-bit register used to enable or
inhibit the timer input capture and output compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
IC1I–IC3I — Input Capture x Interrupt Enable Bits
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable
the corresponding interrupt sources.
Address:
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt
sequence is requested.
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit.
When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt
sequence is requested.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
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OC1I
Bit 7
Figure 8-12. Timer Interrupt Mask 1 Register (TMSK1)
OMx
0
0
0
1
1
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Table 8-3. Timer Output Compare Actions
OLx
OC2I
Programmable Timer
0
1
0
1
6
0
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
OC3I
5
0
Action Taken on Successful Compare
OC4I
4
0
I4/O5I
3
0
IC1I
2
0
Output Compare (OC)
Programmable Timer
IC2I
1
0
Data Sheet
Bit 0
IC3I
0
107

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