mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 57

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.5 Priority Structure
MC68HC711D3 — Rev. 2
MOTOROLA
Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests.
However one I bit related interrupt source may be elevated to the highest I bit
priority in the resolution circuit.
Six interrupt sources are not masked by the I bit in the CCR and have these fixed
priority relationships:
SWI is actually an instruction and has highest priority, other than resets, in that
once the SWI opcode is fetched, no other interrupt can be honored until the SWI
vector has been fetched.
Each of the previous sources is an input to the priority resolution circuit. The
highest I bit masked priority input to the resolution circuit is assigned to be
connected to any one of the remaining I bit related interrupt sources. This
assignment is made under the software control of the HPRIO register. To avoid
timing races, the HPRIO register can be written only while the I bit related interrupts
are inhibited (I bit of CCR is logic 1). An interrupt that is assigned to this higher
priority position is still subject to masking by any associated control bits or by the I
bit in the CCR. The interrupt vector address is not affected by assigning a source
to the higher priority position.
Figure
to normal processing.
how interrupt detection relates to normal opcode fetches.
expansion of a block in
Figure 4-6
resolution of interrupt sources within the SCI subsystem.
1. Reset
2. Clock monitor failure
3. COP failure
4. Illegal opcode
5. SWI
6. XIRQ
Freescale Semiconductor, Inc.
4-4,
For More Information On This Product,
is an expansion of the SCI interrupt block of
Figure
Resets, Interrupts, and Low-Power Modes
Go to: www.freescale.com
4-5, and
Figure 4-4
Figure 4-4
Figure 4-6
shows how the CPU begins from a reset, and
and shows how interrupt priority is resolved.
illustrate the interrupt process as it relates
Resets, Interrupts, and Low-Power Modes
Figure 4-4
Figure 4-5
and shows the
is an
Data Sheet
Interrupts
57