mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 99

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.3.1 Timer Control 2 Register
MC68HC711D3 — Rev. 2
MOTOROLA
of successive edges of an incoming signal, software can determine the period and
pulse width of a signal. To measure period, two successive edges of the same
polarity are captured. To measure pulse width, two alternate polarity edges are
captured.
In most cases, input capture edges are asynchronous to the internal timer counter,
which is clocked relative to the PH2 clock. These asynchronous capture requests
are synchronized to PH2 so that the latching occurs on the opposite half cycle of
PH2 from when the timer counter is being incremented. This synchronization
process introduces a delay from when the edge occurs to when the counter value
is detected. Because these delays offset each other when the time between two
edges is being measured, the delay can be ignored. When an input capture is
being used with an output compare, there is a similar delay between the actual
compare point and when the output pin changes state.
The control and status bits that implement the input capture functions are
contained in the PACTL, TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL
register. Note that this bit is cleared out of reset. To enable PA3 as the fourth input
capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a
fifth output compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is
set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause
edges on the pin to result in input captures. Writing to TI4/O5 has no effect when
the TI4/O5 register is acting as IC4.
Use the control bits of timer control 2 register (TCTL2) to program input capture
functions to detect a particular edge polarity on the corresponding timer input pin.
Each of the input capture functions can be independently configured to detect
rising edges only, falling edges only, any edge (rising or falling), or to disable the
input capture function. The input capture functions operate independently of each
other and can capture the same TCNT value if the input edges are detected within
the same timer count cycle.
EDGxB and EDGxA — Input Capture Edge Control
Address:
There are four pairs of these bits. Each pair is cleared to 0 by reset and must be
encoded to configure the corresponding input capture edge detector circuit. IC4
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
EDG4B
$0021
Bit 7
0
Figure 8-3. Timer Control 2 Register (TCTL2)
Go to: www.freescale.com
EDG4A
Programmable Timer
6
0
EDG1B
5
0
EDG1A
4
0
EDG2B
3
0
EDG2A
2
0
Programmable Timer
EDG3B
1
0
Input Capture
Data Sheet
EDG3A
Bit 0
0
99