mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 78

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface (SCI)
6.7 SCI Registers
6.7.1 SCI Data Register
6.7.2 SCI Control Register 1
Data Sheet
78
This subsection describes the five addressable registers in the SCI.
The SCI data register (SCDR) is a parallel register that performs two functions. It
is the receive data register when it is read, and the transmit data register when it is
written. Reads access the receive data buffer and writes access the transmit data
buffer. Receive and transmit are double buffered.
The SCI control register 1 (SCCR1) provides the control bits that determine word
length and select the method used for the wakeup feature.
R8 — Receive Data Bit 8
T8 — Transmit Data Bit 8
M — Mode Bit
WAKE — Wakeup by Address Mark/Idle Bit
If M bit is set, R8 stores the ninth bit in the receive data character.
If M bit is set, T8 stores ninth bit in transmit data character.
The mode bit selects character format
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
Freescale Semiconductor, Inc.
For More Information On This Product,
U = Unaffected
$002C
$002F
R7/T7
Bit 7
Bit 7
R8
Serial Communications Interface (SCI)
U
Go to: www.freescale.com
Figure 6-4. SCI Control Register 1 (SCCR1)
R6/T6
Figure 6-3. SCI Data Register (SCDR)
T8
U
6
6
R5/T5
5
5
0
0
R4/T4
Unaffected by reset
M
4
4
0
WAKE
R3/T3
3
3
0
R2/T2
2
2
0
0
MC68HC711D3 — Rev. 2
R1/T1
1
1
0
0
MOTOROLA
R0/T0
Bit 0
Bit 0
0
0