mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 72

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Input/Output (I/O) Ports
5.5.2 Port D Data Direction Register
Data Sheet
72
DDD7–DDD0 — Data Direction for Port D
Address:
When port D is a general-purpose I/O port, the DDRD register controls the
direction of the I/O pins as follows:
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as
the slave select (SS) input. In SPI slave mode, DDD5 has no meaning or effect.
In SPI master mode, DDD5 affects port D bit 5 as follows:
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK)
to be inputs, then they are inputs, regardless of the state of DDRD bits 2, 3,
and 4. If the SPI expects port D bits 2, 3, and 4 to be outputs, they are outputs
only if DDRD bits 2, 3, and 4 are set.
Reset:
Read:
Write:
0 = Configures the corresponding port D pin for input only
1 = Configures the corresponding port D pin for output
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
Freescale Semiconductor, Inc.
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DDD7
Bit 7
Figure 5-8. Data Direction Register for Port D (DDRD)
0
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Input/Output (I/O) Ports
DDD6
6
0
DDD5
5
0
DDD4
4
0
DDD3
3
0
DDD2
2
0
MC68HC711D3 — Rev. 2
DDD1
1
0
MOTOROLA
DDD0
Bit 0
0