mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 93

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

7.7.2 SPI Status Register
MC68HC711D3 — Rev. 2
MOTOROLA
SPR1 and SPR0 — SPI Clock Rate Select Bits
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision Bit
Bit 5 — Not implemented
MODF — Mode Fault Bit
Bits 3–0 — Not implemented
Address:
These two serial peripheral rate bits select one of four baud rates to be used as
SCK if the device is a master; however, they have no effect in the slave mode.
SPIF is set upon completion of data transfer between the processor and the
external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt
is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access
the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR
are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set)
followed by an access of SPDR. Refer to
System
Always reads 0.
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR.
Refer to
Always reads 0
Reset:
Read:
Write:
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
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SPIF
Errors.
7.5.4 Slave Select (SS)
Bit 7
0
and SPR0
Serial Peripheral Interface (SPI)
SPR1
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0 0
0 1
1 0
1 1
WCOL
Figure 7-4. SPI Status Register (SPSR)
6
0
Table 7-1. SPI Clock Rates
5
0
0
Divide By
E Clock
16
32
2
4
and
MODF
4
0
7.6 SPI System
7.5.4 Slave Select (SS)
3
0
0
E = 2 MHz (Baud)
Frequency at
Serial Peripheral Interface (SPI)
62.5 kHz
1.0 MHz
500 kHz
125 kHz
2
0
0
Errors.
1
0
0
SPI Registers
and
Data Sheet
7.6 SPI
Bit 0
0
0
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