sed1355 ETC-unknow, sed1355 Datasheet - Page 103

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
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10. t17
Hardware Functional Specification
Issue Date: 99/05/18
Ts
t6
t7
t8
t9
t10
t12
t14
t15
Symbol
min
min
min
min
min
min
min
min
min
t12
t13
t14
t15
t16
t17
t10
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts
= [((REG[07h] bits [3:0])+1)*8] Ts
= [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines
= [((REG[0Ch] bits [2:0])+1)] lines
= [((REG[04h] bits [6:0])+1)*8] Ts
= [((REG[06h] bits [4:0])*8)+1] Ts
= [((REG[04h] bits [6:0])+1)*8] Ts
= [((REG[06h] bits [4:0])+1)*8 - 2] Ts
= [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2]
FPSHIFT period
FPSHIFT pulse width high
FPSHIFT pulse width low
data setup to FPSHIFT falling edge
data hold from FPSHIFT falling edge
FPLINE cycle time
FPLINE pulse width low
FPFRAME cycle time
FPFRAME pulse width low
horizontal display period
FPLINE setup to FPSHIFT falling edge
FPFRAME pulse leading edge to FPLINE pulse
leading edge phase difference
DRDY to FPSHIFT falling edge setup time
DRDY pulse width
DRDY falling edge to FPLINE pulse leading
edge
DRDY hold from FPSHIFT falling edge
FPLINE pulse leading edge to DRDY active
Parameter
Table 7-32: TFT/D-TFD A.C. Timing
note 10
note 2
note 3
note 4
note 5
note 6
note 7
note 8
note 9
0.45
0.45
0.45
0.45
0.45
0.45
0.45
Min
1
Typ
Max
250
Ts (note 1)
X23A-A-001-11
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
SED1355
Page 97