sed1355 ETC-unknow, sed1355 Datasheet - Page 69
sed1355
Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1355.pdf
(509 pages)
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7.2 Clock Input Requirements
Hardware Functional Specification
Issue Date: 99/05/18
Symbol
Symbol
T
T
t
t
t
t
PWH
PWH
PWL
PWL
OSC
OSC
t
t
t
t
f
r
f
r
Table 7-13: Clock Input Requirements for CLKI divided down internally (MCLK = CLKI/2)
90%
10%
Input Clock Period
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
Input Clock Period
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
V
V IL
IH
t r
Note
When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
Table 7-14: Clock Input Requirements for CLKI
t
PWH
Parameter
Parameter
Figure 7-13: Clock Input Requirement
T
OSC
t
f
t
PWL
12.5
11.3
11.3
Min
Min
5.6
5.6
25
Max
Max
5
5
5
5
X23A-A-001-11
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1355
Page 63
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