sed1355 ETC-unknow, sed1355 Datasheet - Page 185

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
5.3.1 Registers
Programming Notes and Examples
Issue Date: 99/04/27
REG[0E] Screen 1 Line Compare Register 0
REG[0F] Screen 1 Line Compare Register 1
REG[13h] Screen 2 Display Start Address Register 0
REG[14h] Screen 2 Display Start Address Register 1
REG[15h] Screen 2 Display Start Address Register 2
Start Addr
Start Addr
Compare
Bit 15
Bit 7
Bit 7
Line
n/a
n/a
Start Addr
Start Addr
Compare
Bit 14
Bit 6
Bit 6
Line
n/a
n/a
The other registers required for split screen operations, [10h] through [12h] (Screen 1 Display Start
Address) and [18h] (Pixel Panning Register), are described in Section 5.2.1 on page 26.
These two registers form a value known as the line compare. When the line compare value is equal
to or greater than the physical number of lines being displayed there is no visible effect on the
display. When the line compare value is less than the number of physically displayed lines, display
operation works like this:
1.
2.
These three registers form the twenty bit offset to the first word in the display buffer that will be
shown in the screen 2 portion of the display.
Screen 1 memory is always displayed first at the top of the screen followed by screen 2 memory.
The start address for the screen 2 image may be lower in memory than that of screen 1 (i.e. screen 2
could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located
several thousand bytes into the display buffer). While not particularly useful, it is possible to set
screen 1 and screen 2 to the same address.
From the end of vertical non-display to the number of lines indicated by line compare the dis-
play data will be from the memory pointed to by the Screen 1 Display Start Address.
After line compare lines have been displayed the display will begin showing data from Screen
2 Display Start Address memory.
Start Addr
Start Addr
Compare
Bit 13
Line
Bit 5
Bit 5
n/a
n/a
Figure 5-7: Screen 2 Display Start Address
Figure 5-6: Screen 1 Line Compare
Start Addr
Start Addr
Compare
Bit 12
Bit 4
Bit 4
Line
n/a
n/a
Start Addr
Start Addr
Start Addr
Compare
Bit 11
Bit 19
Bit 3
Bit 3
Line
n/a
Start Addr
Start Addr
Start Addr
Compare
Bit 10
Bit 18
Bit 2
Bit 2
Line
n/a
Start Addr
Start Addr
Start Addr
Compare
Compare
Bit 17
Bit 1
Bit 9
Bit 1
Bit 9
Line
Line
Start Addr
Start Addr
Start Addr
Compare
Compare
Bit 16
Bit 0
Bit 8
Bit 0
Bit 8
Line
Line
X23A-G-003-05
SED1355
Page 29