sed1355 ETC-unknow, sed1355 Datasheet - Page 88

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 82
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SED1355
X23A-A-001-11
Symbol
t10
t11
t12
t13
t14
t1
t2
t3
t4
t5
t6
t7
t8
t9
Ts
t1
t4
t5
t6
t9
min
min
min
min
min
Sync Timing
Data Timing
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
= t4
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
=[(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 28] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts
FPFRAME setup to FPLINE pulse trailing edge
FPFRAME hold from FPLINE pulse trailing edge
FPLINE pulse width
FPLINE period
MOD delay from FPLINE pulse trailing edge
FPSHIFT falling edge to FPLINE pulse leading edge
FPLINE pulse trailing edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT falling edge to FPLINE pulse trailing edge
FPLINE pulse trailing edge to FPSHIFT rising edge
FPSHIFT pulse width high
FPSHIFT pulse width low
UD[3:0], setup to FPSHIFT falling edge
UD[3:0], hold from FPSHIFT falling edge
min
- 14Ts
FPFRAME
FPSHIFT
FPLINE
FPLINE
UD[3:0]
MOD
Figure 7-29: 4-Bit Single Color Passive LCD Panel A.C. Timing
Table 7-25: 4-Bit Single Color Passive LCD Panel A.C. Timing
Parameter
t6
t5
t9
t1
t10
t3
t7
t2
t10 + t11
t13
note 2
note 3
note 4
note 5
note 6
0.45
0.45
0.45
0.45
Min
14
21
9
1
1
t4
t14
Epson Research and Development
t11
Hardware Functional Specification
Typ
t8
2
t12
Vancouver Design Center
Max
Issue Date: 99/05/18
Ts (note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts