sed1355 ETC-unknow, sed1355 Datasheet - Page 259

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

SED1355F0A Register Summary
SED1355F0A Register Summary
Page 1
Polarity Slct
Status (RO)
Polarity Slct
REG[00h] R
REG[01h] M
REG[02h] P
REG[03h] M
REG[04h] H
REG[05h] H
REG[06h] HRTC/FPLINE S
REG[07h] HRTC/FPLINE P
REG[08h] V
REG[09h] V
REG[0Ah] V
REG[0Bh] VRTC/FPFRAME S
REG[0Ch] VRTC/FPFRAME P
REG[0Dh] D
Hardware
REG[0Eh] S
REG[0Fh] S
REG[10h] S
EL Panel
Portrait
Enable
Enable
HRTC
VNDP
VRTC
Mode
Bit 5
n/a
Bit 7
Bit 7
Bit 7
n/a
n/a
n/a
n/a
n/a
n/a
n/a
2
EVISION
ANEL
ORIZONTAL
ORIZONTAL
Polarity Slct
ERTICAL
ERTICAL
Polarity Slct
CREEN
CREEN
CREEN
EMORY
OD
ERTICAL
ISPLAY
FPFRAME
Simultaneous Display
FPLINE
Bit 4
Bit 2
R
Bit 6
Bit 6
Bit 1
Bit 6
Bit 6
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
ATE
T
Option Select
YPE
1 L
1 L
1 D
C
M
C
D
D
N
ONFIGURATION
ODE
R
ODE
ISPLAY
ISPLAY
ON
INE
INE
ISPLAY
R
EGISTER
D
N
Refresh Rate
EGISTER
ISPLAY
ON
-D
R
R
C
C
-D
TART
ULSE
ISPLAY
EGISTER
OMPARE
OMPARE
EGISTER
Panel Data Width
H
H
S
Bit 3
Bit 1
Bit 1
Bit 5
Bit 5
ISPLAY
Bit 5
Bit 5
Bit 5
Bit 0
Bit 5
Bit 5
n/a
n/a
n/a
n/a
n/a
n/a
TART
ULSE
EIGHT
EIGHT
TART
Product Code
W
P
W
IDTH
OSITION
Vertical Display Height = (REG + 1)
P
IDTH
R
5
ERIOD
P
W
R
R
1
A
R
R
P
EGISTER
OSITION
EGISTER
EGISTER
3
IDTH
DDRESS
ERIOD
EGISTER
EGISTER
R
(For SED1355: Product Code=000011b, Revision Code=00b)
R
Horizontal Display Width = 8(REG + 1)
EGISTER
Screen 1 Line Compare
Screen 1 Start Address
EGISTER
Vertical Non-Display Period (VNDP) = (REG + 1)
R
R
R
Bit 2
Bit 0
Bit 0
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 2
Bit 4
Bit 4
EGISTER
n/a
n/a
EGISTER
n/a
n/a
VRTC/FPFRAME Start Position = (REG + 1)
EGISTER
R
R
0
1
R
EGISTER
4
0
1
EGISTER
EGISTER
Bit-per-pixel Select
Horizontal Non-Display Period = 8(REG + 1)
HRTC/FPLINE Start Position = 8(REG + 1)
Format Slct
Panel Data
0
Bit 1
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 1
Bit 3
Bit 3
n/a
n/a
n/a
n/a
HRTC/FPLINE Pulse Width = 8(REG + 1)
MOD Rate
WE# Control
VRTC/FPFRAME Pulse Width = (REG + 1)
Color/Mono
Panel Slct
6
Bit 0
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 0
Bit 2
Bit 2
n/a
n/a
CRT Enable LCD Enable
Dual/Single
Panel Slct
Screen 1 Line Compare
Vertical Display Height
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
n/a
1/0
1/0
Revision Code
TFT/Passive
LCD Pan Slct
Memory
Type
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Power Save
Reserved
Status RO
REG[11h] S
REG[12h] S
REG[13h] S
REG[14h] S
REG[15h] S
REG[16h] M
REG[17h] M
REG[18h] P
REG[19h] C
REG[1Ah] P
REG[1Bh] M
REG[1Ch] MD C
REG[1Dh] MD C
REG[1Eh] G
REG[1Fh] G
REG[20h] G
REG[21h] G
Interface
Disable
Control
Status
MD15
Status
Bit 15
Bit 15
Host
MD7
GPO
Bit 7
Bit 7
Bit 3
n/a
n/a
n/a
n/a
n/a
n/a
CREEN
CREEN
CREEN
CREEN
CREEN
IXEL
EMORY
EMORY
LOCK
OWER
ENERAL
ENERAL
ENERAL
ISCELLANIOUS
ENERAL
Screen 2 Pixel Panning
Status
Status
Bit 14
Bit 14
MD14
MD6
Bit 6
Bit 6
Bit 2
n/a
n/a
n/a
P
n/a
n/a
n/a
ONFIGURATION
ONFIGURATION
n/a
n/a
n/a
n/a
C
ANNING
S
1 D
1 D
2 D
2 D
2 D
A
A
ONFIGURATION
AVE
IO P
IO P
IO P
IO P
DDRESS
DDRESS
ISPLAY
ISPLAY
ISPLAY
ISPLAY
ISPLAY
C
INS
INS
INS
INS
R
ONFIGURATION
R
EGISTER
EGISTER
Status
Status
C
C
C
C
Bit 13
Bit 13
MD13
O
O
S
S
S
Bit 5
S
S
Bit 5
Bit 1
MD5
ONFIGURATION
ONTROL
ONTROL
n/a
n/a
n/a
n/a
n/a
n/a
ONFIGURATION
n/a
n/a
n/a
n/a
TART
TART
TART
TART
TART
FFSET
FFSET
R
R
EADBACK
EADBACK
R
EGISTER
A
A
A
A
A
R
R
DDRESS
DDRESS
DDRESS
DDRESS
DDRESS
R
R
EGISTER
EGISTER
EGISTER
EGISTER
Screen 1 Start Address
Screen 2 Start Address
Screen 2 Start Address
Memory Address Offset
R
EGISTER
R
Status
R
MD12
Status
Bit 12
Bit 12
Bit 4
Bit 4
Bit 0
MD4
n/a
n/a
n/a
n/a
n/a
n/a
EGISTER
EGISTER
n/a
n/a
n/a
n/a
R
R
R
R
R
R
R
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
0
1
0
1
0
1
LCD Power
GPIO3 Pin
GPIO3 Pin
IO Config
IO Status
1
0
Disable
Status
MD11
Status
1
Bit 11
2
Bit 19
0
1
Bit 11
2
Bit 19
Bit 3
Bit 3
Bit 3
MD3
n/a
n/a
n/a
n/a
n/a
Suspend Refresh Select
Divide Slct
GPIO2 Pin
GPIO2 Pin
IO Config
IO Status
Screen 1 Start Address
Screen 2 Start Address
Screen 1 Pixel Panning
MCLK
Status
Status
Bit 10
Bit 18
Bit 10
Bit 18
Bit 10
MD10
MD2
Bit 2
Bit 2
Bit 2
Bit 1
n/a
n/a
n/a
Memory Address Offset
GPIO1 Pin
GPIO1 Pin
IO Config
IO Status
Status
Status
Bit 17
Bit 17
PCLK Divide
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 1
Bit 0
MD1
MD9
n/a
n/a
n/a
8
Suspend En
Half Frame
Software
Disable
Bit 16
Bit 16
Buffer
Status
Status
7
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 0
MD0
MD8
n/a
n/a
n/a
n/a
Slct
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
Notes
1 These bits are used to identify the SED1355. For the SED1355 the product code should be 3. The host interface
2 N/A bits should be written 0.
Display FIFO
REG[22h] P
Reserved
REG[23h] P
REG[24h] L
REG[26h] L
REG[27h] I
REG[28h] C
REG[29h] C
Reserved
REG[2Ah] C
REG[2Bh] C
Reserved
REG[2Ch] I
REG[2Dh] I
REG[2Eh] I
REG[2Fh] I
REG[30h] I
REG[31h] A
Bit 7 WO
Disable
must be enabled before reading this register (set REG[1B] b7=0).
Reserved bits must be written 0.
Bit 15
Bit 15
Bit 7
Bit 3
Bit 1
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Ink/Cursor Mode
NK
NK
NK
NK
NK
NK
CPU to Memory Wait State
OOK
OOK
ERFORMANCE
ERFORMANCE
URSOR
URSOR
LTERNATE
URSOR
URSOR
/C
/C
/C
/C
/C
/C
Look-Up Table Data
Bit 14
Bit 14
RC Timing Value
Bit 1
-U
Bit 6
-U
Bit 2
URSOR
Bit 0
Bit 6
Bit 6
Bit 6
Bit 6
URSOR
Bit 6
Bit 6
Bit 1
URSOR
URSOR
URSOR
URSOR
n/a
n/a
P
P
X P
X P
Y P
Y P
T
T
ABLE
ABLE
FRM R
OSITION
OSITION
C
OSITION
OSITION
C
S
C
C
C
ONTROL
OLOR
TART
OLOR
OLOR
OLOR
E
E
NHANCEMENT
NHANCEMENT
A
D
DDRESS
ATA
Bit 13
Bit 13
Bit 0
Bit 5
Bit 1
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
EGISTER
Bit 5
Bit 0
n/a
n/a
n/a
A
1 R
R
R
0 R
0 R
1 R
R
R
DDRESS
Alternate Frame Range Modulation Select
EGISTER
EGISTER
EGISTER
EGISTER
9
R
R
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
Ink/Cursor Start Address Select
R
EGISTER
S
R
R
Look-Up Table Address
RAS#-to-
Delay
0
1
ELECT
0
1
EGISTER
EGISTER
CAS#
Bit 12
0
1
Bit 12
0
1
Bit 4
Bit 4
Bit 0
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
n/a
Cursor X Position
n/a
Cursor Y Position
n/a
Cursor Color 0
Cursor Color 0
Cursor Color 1
Cursor Color 1
10
R
EGISTER
0
1
RAS# Precharge
Bit 11
Bit 11
Bit 1
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
n/a
n/a
n/a
Display FIFO Threshold
12
Cursor High Threshold
Bit 10
Bit 10
11
X23A-R-001-02
Bit 0
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
n/a
n/a
n/a
Timing
Reserved
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 1
Bit 1
Cursor X Position
Cursor Y Position
98/09/15
n/a
Reserved
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 0
n/a
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW