sed1355 ETC-unknow, sed1355 Datasheet - Page 117

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
bits 7-4
bits 3-0
8.2.5 Clock Configuration Register
bit 7
bit 2
Hardware Functional Specification
Issue Date: 99/05/18
Pixel Panning Register
REG[18h]
Screen 2
Pixel Panning
Bit 3
Clock Configuration Register
REG[19h]
Reserved
Screen 2
Pixel Panning
Bit 2
n/a
Display Mode
15/16 bpp
Note
This register is used to control the horizontal pixel panning of Screen 1 and Screen 2. Each screen
can be independently panned to the left by programming its respective Pixel Panning Bits to a non-
zero value. The value represents the number of pixels panned. The maximum pan value is dependent
on the display mode.
Smooth horizontal panning can be achieved by a combination of this register and the Display Start
Address registers.
See “Section 10 Display Configuration” for details.
Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
Reserved
This bit must be set to 0.
MCLK Divide Select
When this bit = 1 the MCLK frequency is half of its source frequency.
When this bit = 0 the MCLK frequency is equal to its source frequency.
The MCLK frequency should always be set to the maximum frequency allowed by the DRAM; this
provides maximum performance and minimum overall system power consumption.
1 bpp
2 bpp
4 bpp
8 bpp
There must always be a source clock at CLKI.
Screen 2
Pixel Panning
Bit 1
n/a
Table 8-8: Pixel Panning Selection
Screen 2
Pixel Panning
Bit 0
n/a
Maximum Pan Value
16
8
4
1
0
Screen 1
Pixel Panning
Bit 3
n/a
Screen 1
Pixel Panning
Bit 2
MCLK Divide
Select
Pixel Panning Bits active
Bits [3:0]
Bits [2:0]
Bits [1:0]
none
Bit 0
Screen 1
Pixel Panning
Bit 1
PCLK Divide
Select Bit 1
Screen 1
Pixel Panning
Bit 0
PCLK Divide
Select Bit 0
X23A-A-001-11
SED1355
Page 111
RW
RW