sed1355 ETC-unknow, sed1355 Datasheet - Page 408

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 12
3.2 PC Card Host Bus Interface Signals
SED1355
X23A-G-005-05
The SED1355 PC Card host bus interface is designed to support processors which interface
the SED1355 through the PC Card bus.
The SED1355 PC Card host bus interface requires the following signals from the PC Card
bus.
• BUSCLK is a clock input which is required by the SED1355 host bus interface. It is
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the PC
• M/R# (memory/register) selects between memory or register access. It may be
• Chip Select (CS#) must be driven low whenever the SED1355 is accessed by the PC
• WE1# and RD/WR# connect to -CE2 and -CE1 (the byte enables for the high-order and
• RD# connects to -OE (the read enable signal from the PC Card bus).
• WE0# connects to -WE (the write enable signal from the PC Card bus).
• WAIT# is a signal output from the SED1355 that indicates the PC Card bus must wait
• The Bus Start (BS#) signal is not used for the PC Card host bus interface and should be
• The RESET# (active low) input of the SED1355 may be connected to the PC Card
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock. Since PC Card signalling is independent of any clock, BUSCLK can come from
any oscillator already implemented. For example, the source for the CLKI input of the
SED1355 may be used.
Card address (A[20:0]) and data bus (D[15:0]), respectively. MD4 must be set to select
little endian mode upon reset.
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
Card bus.
low-order bytes). They are driven low when the PC Card bus is accessing the SED1355.
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since PC Card
bus accesses to the SED1355 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the SED1355 internal registers and/or
display buffer. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. For PC Card applications, this signal should
be set active low using the MD5 configuration input.
tied high (connected to V
RESET (active high) using an inverter.
DD
).
Epson Research and Development
Interfacing to the PC Card Bus
Vancouver Design Center
Issue Date: 99/05/05