sed1355 ETC-unknow, sed1355 Datasheet - Page 92

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 86
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SED1355
X23A-A-001-11
Symbol
t10
t11
t12
t13
t14
Ts
t1
t3
t5
t6
t7
t1
t2
t3
t4
t5
t6
t7
t8
t9
min
min
min
min
min
Data Timing
Sync Timing
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
= t3
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 28] Ts
= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts
FPFRAME setup to FPLINE pulse trailing edge
FPFRAME hold from FPLINE pulse trailing edge
FPLINE period
FPLINE pulse width
MOD delay from FPLINE pulse trailing edge
FPSHIFT falling edge to FPLINE pulse leading edge
FPSHIFT falling edge to FPLINE pulse trailing edge
FPLINE pulse trailing edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
UD[3:0], LD[3:0] setup to FPSHIFT falling edge
UD[3:0], LD[3:0] hold to FPSHIFT falling edge
FPLINE pulse trailing edge to FPSHIFT rising edge
min
- 14Ts
FPFRAME
Figure 7-33: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)
FPSHIFT
Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)
UD[3:0]
LD[3:0]
FPLINE
FPLINE
MOD
Parameter
t6
t5
t7
t1
t14
t4
t8
t2
t12
t14 + 2
note 2
note 3
note 4
note 5
note 6
Min
1
14
20
9
2
1
1
1
1
t3
t13
t11
Epson Research and Development
Hardware Functional Specification
Typ
t9
2
t10
Vancouver Design Center
Max
Issue Date: 99/05/18
Ts (note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts