sed1355 ETC-unknow, sed1355 Datasheet - Page 106

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 100
8 Registers
8.1 Register Mapping
8.2 Register Descriptions
8.2.1 Revision Code Register
bits 7-2
bits 1-0
SED1355
X23A-A-001-11
Revision Code Register
REG[00h]
Product Code
Bit 5
Product Code
Bit 4
CS#
0
0
1
The SED1355 registers are memory mapped. The system addresses the registers through the CS#,
M/R#, and AB[5:0] input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address
bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] =
000001. See the table below:
Unless specified otherwise, all register bits are reset to 0 during power-on. Reserved bits should be
written 0 when programming unless otherwise noted.
Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip. The product code for the
SED1355 is 000011.
Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip. The revision code for the
SED1355F0A is 00.
Product Code
Bit 3
M/R#
X
0
1
Product Code
Bit 2
Table 8-1: SED1355 Addressing
Register access:
• REG[00h] is addressed when AB[5:0] = 0
• REG[01h] is addressed when AB[5:0] = 1
• REG[n] is addressed when AB[5:0] = n
Memory access: the 2M byte Display Buffer is addressed by
AB[20:0]
SED1355 not selected
Product Code
Bit 1
Access
Product Code
Bit 0
Epson Research and Development
Revision
Code Bit 1
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18
Revision
Code Bit 0
RO