sed1355 ETC-unknow, sed1355 Datasheet - Page 441

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
2.2.1 Normal (Non-Burst) Bus Transactions
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/05/05
TSIZ[0:1], AT[0:3]
A data transfer is initiated by the bus master by placing the memory address on address
lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several
control signals are also provided with the memory address:
• TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit.
• RD/WR -- set high for read cycles and low for write cycles.
• AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being
When the peripheral device being accessed has completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle to complete the bus transaction. Once TA has
been asserted, the MPC821 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
Figure 2-1: “Power PC Memory Read Cycle” on page 9 illustrates a typical memory read
cycle on the Power PC system bus.
SYSCLK
RD/WR
D[0:31]
A[0:31]
attempted.
Transfer Start
TS
TA
Figure 2-1: Power PC Memory Read Cycle
Wait States
Complete
Transfer
Next Transfer
Sampled when TA low
Starts
X23A-G-008-03
SED1355
Page 9