sed1355 ETC-unknow, sed1355 Datasheet - Page 154

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 148
15 Power Save Modes
SED1355
X23A-A-001-11
Register Access Possible?
Memory Access Possible?
LUT Access Possible?
Host Interface outputs
Display Active?
CRT/DAC outputs
DRAM outputs
Function
LCD outputs
LCDPWR
Pins
Three power save modes are incorporated into the SED1355 to meet the important need for power
reduction in the hand-held device market.
1.
2.
Refresh method is selectable by REG[1Ah]. Supported methods are CBR refresh, self-refresh
or no refresh at all.
The FPFRAME and FPLINE signals are set to their inactive states during power-down. The in-
active states are determined by REG[07h] bit 6 and REG[0Ch] bit 6. A problem may occur if
the inactive state is high (typical TFT/D-TFD configuration) and power is removed from the
LCD panel.
For software suspend the problem can be solved in the following manner. At power-down, first
enable software suspend, then wait ~120 VNDP, and lastly reverse the polarity bits. At power-
up, first disable software suspend, then revert the polarity bits back to the configuration state.
For hardware suspend an external hardware solution would be to use an AND gate on the sync
signal. One input of the AND gate is connected to a sync signal, the other input would be tied
to the panel’s logic power supply. When the panel’s logic power supply is removed, the sync
signal is forced low.
Table 15-1: Power Save Mode Function Summary
Table 15-2: Pin States in Power-save Modes
(LCDEnable = 1)
(LCDEnable = 1)
(CRTEnable = 1)
(Active)
Normal
Active
Active
Active
Active
(Active)
Normal
On
Yes
Yes
Yes
Yes
LCDEnable = 0
CRTEnable = 0
CBR Refresh
Forced Low
No Display
LCDEnable = 0
CRTEnable = 0
Disabled
Active
No Display
only
Off
Power Save Mode (PSM)
Yes
Yes
Yes
No
Pin State
2
Refresh Only
Forced Low
Software
Suspend
Disabled
Active
Off
Software
Suspend
Yes
Yes
No
No
Epson Research and Development
2
Hardware Functional Specification
1
Refresh Only
Forced Low
Hardware
Vancouver Design Center
Suspend
Disabled
Disabled
Off
Hardware
Issue Date: 99/05/18
Suspend
No
No
No
No
2
1