sed1355 ETC-unknow, sed1355 Datasheet - Page 277

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
Comments
1355CFG Configuration Program
Issue Date: 98/10/30
• It is assumed that the 1355CFG user is familiar with SED1355 hardware and software. Refer to
• 1355CFG verifies that the given configuration meets the limitations in the hardware specifica-
• When configuring either the CRT or TFT/D-TFD panel, the PClk must be the same as the
• 1355CFG does not support 50ns FPM-DRAM.
• 1355CFG programs TFT/D-TFD panels with the same VESA timings as a CRT, so the CRT
• For simultaneous display, select a CRT VESA mode, and use the CRT’s frame rate for the
Resolution
the SED1355 Functional Hardware Specification, document number X23A-A-001-xx, and the
SED1355 Programming Notes and Examples, document number X23A-G-003-xx for details.
tion. Part of this verification process is as follows:
required VESA frequency for the given VESA mode. The following VESA modes are supported:
640x480
800x600
restrictions shown in the hardware specification also apply to TFT/D-TFD panels. Consequently
for TFT/D-TFD panels, use the CRT frame rate and CRT PCLK as described above.
panel’s frame rate.
1.
2.
3.
4.
The divide ratio for the source clock/MClk is determined based on Table 14-3: Example
Frame Rates with Ink Disabled from the Functional Hardware Specification. According to
this table, MClk cannot exceed 40 MHz for 50ns EDO-DRAM, MClk cannot exceed 33
MHz for 60ns EDO-DRAM, and MClk cannot exceed 25 MHz for 60ns FPM-DRAM. If
MClk exceeds the maximum value, the MCLK value is set to the source clock divided by
two (MClk = source clock / 2). Otherwise the MCLK value is set to the source clock
(MClk = source clock). 1355CFG shows the MClk value on the General Page.
The divide ratio for MClk/PClk is determined based on Table 14-1: Maximum PCLK Fre-
quency with EDO-DRAM and Table 14-2: Maximum PCLK Frequency with FPM-DRAM.
Once this ratio is determined, PClk = MClk / ratio. Note that there are two PClk divide ra-
tios based on the three display modes: panel, CRT, and simultaneous display (CRT and si-
multaneous display use the same ratio). 1355CFG shows the PClk values for these three
modes on the General Page.
The HNDP and VNDP values are calculated based on the desired frame rate for each of
the three modes (panel, CRT, simultaneous), the display’s HDP (X resolution), VDP (Y
resolution), and maximum PCLK as calculated in step 3.
If it is not possible to reach the desired frame rate within 5%, an error message is shown
when saving the configuration.
Rate (Hz)
Frame
60
72
75
85
56
60
FrameRate
PCLK (MHz) Supported DRAM Types
25.175
31.500
31.500
36.000
36.000
40.000
=
---------------------------------------------------------------------------------------- -
HDP
+
50ns EDO, 60ns EDO,
70ns EDO, 60ns FPM
50ns EDO, 60ns EDO
50ns EDO, 60ns EDO
50ns EDO
50ns EDO
50ns EDO
HNDP
PCLK
VDP
+
VNDP
X23A-B-001-02
SED1355
Page 17