sed1355 ETC-unknow, sed1355 Datasheet - Page 123

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
bits 3-2
bits 1-0
bit 0
Hardware Functional Specification
Issue Date: 99/05/18
DRAM Type
EDO
FPM
REG[22h] bits [3:2]
Optimal DRAM Timing
The following table contains the optimally programmed values of N
DRAM types, at maximum MCLK frequencies.
RAS# Precharge Timing Value (N
Minimum Memory Timing for RAS# precharge
These bits select the DRAM RAS# Precharge timing parameter, t
(N
assume an MCLK duty cycle of 50 +/- 5%.
N
The resulting t
t
t
Reserved
These bits must be set to 0.
Table 8-15: Optimal N
Reserved
This reserved bit must be set to 0.
RP
RP
00
01
10
11
RP
RP
DRAM Speed
) of MCLK periods (T
(ns)
50
60
70
60
70
RC
= 1
= 1.5
= 2
= (N
= (N
Table 8-14: RAS Precharge Timing Select
is related to N
RP
RP
RC
) T
, N
+ 0.5) T
RP
(ns)
M
T
25
30
33
40
50
M
M
, and N
) used to create t
if (t
if 1
if (t
Reserved
M
RP
RP
RP
N
RP
RCD
1.5
as follows:
(t
2
1
/T
/T
RP
) Bits [1:0]
RP
M
M
if FPM refresh cycle and N
for all other
values at maximum MCLK frequency
/T
) < 1
)
(#MCLK)
M
N
1.45
) < 1.45
4
4
5
4
3
RC
RP
– see the following formulae. Note, these formulae
RAS# Precharge Width (t
(#MCLK)
N
1.5
1.5
1.5
1.5
2
RP
Reserved
RP
RP
RC
. These bits specify the number
1.5
2
1
= 1 or 2
, N
RP
(#MCLK)
N
, and N
RCD
2
2
2
2
1
RP
RCD
)
X23A-A-001-11
for different
SED1355
Page 117