sed1355 ETC-unknow, sed1355 Datasheet - Page 165

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
Programming Notes and Examples
Issue Date: 99/04/27
Register
[0B]
[0C]
[0D]
[0E]
[0F]
[1A]
[1C]
[1D]
[1E]
[1F]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
0000 0000 FPFRAME start position - only required for CRT or TFT/D-TFD
0000 0000 FPFRAME polarity set to active high
0000 1100
1111 1111 Line compare (Regs[0Eh] and[0Fh] set to maximum allowable
0000 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0100 0000 Memory Address Offset (Regs [17h] [16h])
0000 0001
0000 0000 Set pixel panning for both screens to 0
0000 0001
0000 0000 Enable LCD Power
0000 0000 MD Configuration Readback - we write a 0 here to keep the
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Value
Display mode - hardware portrait mode disabled, 8 bpp and
LCD disabled, enable LCD in last step of this example.
value. We can change this later if we want a split screen.
Screen 1 Start Address (Regs [10h], [11h], and [12h]) set to 0.
This will start the display in the first byte of the display buffer.
Screen 2 Start Address (Regs [13h], [14h], and [15h]) to offset
0. Screen 2 Start Address in not used at this time.
- 640 pixels = 640 bytes = 320 words = 140h words
Note: When setting a horizontal resolution greater than 767
pixels, with a color depth of 15/16 bpp, the Memory Offset
Registers (REG[16h], REG[17h]) must be set to a virtual
horizontal pixel resolution of 1024.
Clock Configuration - set PClk to MClk/2 - the specification says
that for a dual color panel the maximum PClk is MClk/2
register configuration logic simpler
General I/O Pins - set to zero.
General I/O Pins Control - set to zero.
Table 2-1: SED1355 Initialization Sequence (Continued)
Notes
‘
See Also
X23A-G-003-05
SED1355
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