sed1355 ETC-unknow, sed1355 Datasheet - Page 35

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

LCAS#
UCAS#
WE#
RAS#
MD[15:0]
Epson Research and Development
Vancouver Design Center
5.2.2 Memory Interface
Hardware Functional Specification
Issue Date: 99/05/18
Pin Name
O
O
O
O
IO
Type
51
52
54
53
34, 36, 38,
40, 42, 44,
46, 48, 49,
47, 45, 43,
41, 39, 37,
35
Pin #
CO1
CO1
CO1
CO1
C/TS
1D
Cell
Table 5-2: Memory Interface Pin Descriptions
1
1
1
1
Hi-Z
RESET#
State
• For dual-CAS# DRAM, this is the column address strobe for the
• For single-CAS# DRAM, this is the column address strobe (CAS#).
See “Memory Interface Pin Mapping” for summary. See Memory
Interface Timing for detailed functionality.
This is a multi-purpose pin:
• For dual-CAS# DRAM, this is the column address strobe for the
• For single-CAS# DRAM, this is the write enable signal for the upper
See “Memory Interface Pin Mapping” for summary. See Memory
Interface Timing for detailed functionality.
• For dual-CAS# DRAM, this is the write enable signal (WE#).
• For single-CAS# DRAM, this is the write enable signal for the lower
See “Memory Interface Pin Mapping” for summary. See Memory
Interface Timing for detailed functionality.
Row address strobe - see Memory Interface Timing for detailed
functionality.
Bi-Directional memory data bus.
During reset, these pins are inputs and their states at the rising edge of
RESET# are used to configure the chip - see Summary of
Configuration Options . Internal pull-down resistors (typical values of
100K
External pull-up resistors can be used to pull the reset states to 1.
See Memory Interface Timing for detailed functionality.
lower byte (LCAS#).
upper byte (UCAS#).
byte (UWE#).
byte (LWE#).
at 5V/3.3V respectively) pull the reset states to 0.
Description
X23A-A-001-11
SED1355
Page 29