sed1355 ETC-unknow, sed1355 Datasheet - Page 260

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

SED1355F0A Register Summary
3 DRAM Refresh Rate Select
4 Panel Data Width Selection
5 Simultaneous Display Option Selection
6 Number of Bits-Per-Pixel Selection
7 PCLK Divide Selection
8 Suspend Refresh Selection
9 Minimum Memory Timing Selection
10 RAS#-to-CAS# Delay Timing Select
Page 2
DRAM Refresh
Rate Select Bits
[2:0]
Panel Data Width Bits
[1:0]
Simultaneous Display Option Select Bits
[1:0]
Bit-Per-Pixel Select Bits [2:0]
PCLK Divide Select Bits [1:0]
Suspend Refresh Select Bits [1:0]
REG[22h] Bits [6:5]
REG[22h] Bit 4
000
001
010
011
100
101
110
111
00
01
10
11
00
01
10
11
0
1
00
01
10
11
110-111
00
01
10
11
00
01
1x
CLKI Frequency
Divisor
000
001
010
011
100
101
Passive LCD Panel Data Width
Size
1024
2048
4096
8192
128
256
512
64
N
N
RCD
RC
Reserved
16-bit
4-bit
8-bit
Reserved
2
1
5
4
3
Example Refresh
Rate for CLKI =
33MHz
Simultaneous Display Mode
MCLK: PCLK Frequency Ratio
DRAM Refresh Type
520 kHz
260 kHz
130 kHz
65 kHz
33 kHz
16 kHz
8 kHz
4 kHz
CAS-before-RAS (CBR) Refresh
Color Depth (Bit-Per-Pixel)
RAS#-to-CAS# Delay (t
Even Scan Only
Line Doubling
Self-Refresh
Minimum Random Cycle
Width (t
TFT Panel Data Width Size
No Refresh
Interlace
Normal
Reserved
1: 1
2: 1
3: 1
4: 1
15 bpp
16 bpp
1 bpp
2 bpp
4 bpp
8 bpp
Example period for
256 refresh cycles at
CLKI = 33MHz
RC
Reserved
Reserved
2
1
12-bit
16-bit
)
9-bit
0.5 ms
5
4
3
16 ms
32 ms
64 ms
1 ms
2 ms
4 ms
8 ms
RCD
)
11 RAS Precharge Timing Select
12 Ink/Cursor Start Address Encoding
REG[22h] Bits [3:2]
Ink/Cursor Start Address Bits [7:0]
00
01
10
11
n = 255...1
0
N
RP
Reserved
1.5
2
1
Start Address (Bytes)
Display Buffer Size – (n x 8192)
Display Buffer Size – 1024
RAS Precharge Width (t
Reserved
1.5
2
1
RP
)
X23A-R-001-02
98/09/15