sed1355 ETC-unknow, sed1355 Datasheet - Page 468

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 12
4.2 SED1355 Configuration
SED1355
X23A-G-010-03
MD0
MD[3:1]
MD4
MD5
MD11
MD12
Pin Name
SED1355
111 = Toshiba TX3912 host bus interface if Alternate host bus interface is selected
Little Endian
WAIT# is active high (1 = insert wait state)
Alternate host bus interface selected
BUSCLK input divided by two: use with DCLKOUT
= configuration for Toshiba TX3912 host bus interface
The host interface control signals of the SED1355 are asynchronous with respect to the
SED1355 bus clock. This gives the system designer full flexibility to choose the
appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks
should be the same, whether to use DCLKOUT as clock source, and whether an external or
internal clock divider is needed, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1356 clock frequencies.
The SED1355 also has internal CLKI dividers providing additional flexibility.
The SED1355 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
SED1355 Hardware Functional Specification, document number X23A-A-001-xx.
The table below shows those configuration settings relevant to the Toshiba TX3912 host
bus interface.
8-bit host bus interface
Table 4-1: SED1355 Configuration for Direct Connection
Value on this pin at rising edge of RESET# is used to configure:
1 (V
DD
)
16-bit host bus interface
Big Endian
WAIT# is active low (0 = insert wait state)
Primary host bus interface selected
BUSCLK input not divided: use with external oscillator
Interfacing to the Toshiba MIPS TX3912 Processor
Epson Research and Development
0 (V
SS
)
Vancouver Design Center
Issue Date: 99/05/05