sed1355 ETC-unknow, sed1355 Datasheet - Page 18

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sed1355

Manufacturer Part Number
sed1355
Description
Sed1355 Embedded Ramdac Lcd/crt Controller
Manufacturer
ETC-unknow
Datasheet

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Page 12
2 Features
2.1 Memory Interface
2.2 CPU Interface
SED1355
X23A-A-001-11
• 16-bit DRAM interface:
• Memory size options:
• Performance Enhancement Register to tailor the memory control output timing for the DRAM
• Supports the following interfaces:
• Supports the following interface with external logic:
• One-stage write buffer for minimum wait-state CPU writes.
• Registers are memory-mapped – the M/R# pin selects between the display buffer and register
• The complete 2M byte display buffer address space is addressable as a single linear address
• EDO-DRAM up to 40MHz data rate (80M bytes/sec.).
• FPM-DRAM up to 25MHz data rate (50M bytes/sec.).
• 512K bytes using one 256K 16 device.
• 2M bytes using one 1M 16 device.
device.
• 8/16-bit SH-4 bus interface.
• 8/16-bit SH-3 bus interface.
• 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers.
• 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers.
• Philips PR31500/PR31700 (MIPS).
• Toshiba TX3912 (MIPS)
• 16-bit Power PC (MPC821) microprocessor.
• 16-bit Epson E0C33 microprocessor.
• PC Card (PCMCIA).
• StrongARM (PC Card).
• NEC VR41xx (MIPS).
• ISA bus.
• GX486 microprocessor.
address space.
space through the 21-bit address bus.
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 99/05/18

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