sed1355 ETC-unknow, sed1355 Datasheet - Page 122

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 116
bits 6-5
bit 4
SED1355
X23A-A-001-11
REG[22h] bits [6:5]
REG[22h] bit 4
RC Timing Value (N
These bits select the DRAM random-cycle timing parameter, t
(N
t
value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N
N
The resulting t
t
RAS#-to-CAS# Delay Value (N
This bit selects the DRAM RAS#-to-CAS# delay parameter, t
(N
access time, t
N
Note that for EDO-DRAM and N
N
The resulting t
t
t
t
t
RAS
RC
RCD
RCD
RCD
RCD
00
01
10
11
RC
RC
RCD
RCD
0
1
RC
RCD
, the RAS pulse width. Use the following two formulae to calculate N
) of MCLK periods (T
. This is done to satisfy the CAS# address setup time, t
) of MCLK periods (T
= Round-Up((t
= 2
= Round-Up(t
= Round-Up(t
RAC
Table 8-12: Minimum Memory Timing Selection
Table 8-13: RAS#-to-CAS# Delay Timing Select
RC
RC
= Round-Up (t
= Round-Up (t
= Round-Up (t
= (N
= (N
= (1.5) T
= (N
= (N
. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
is related to N
is related to N
RC
RCD
RCD
RCD
RC
) T
) Bits [1:0]
) T
) T
M
+ 0.5) T
RAC
RAC
M
RAC
M
M
M
M
) used to create t
/T
/T
RC
RAS
RAS
) used to create t
+ 5)/T
Reserved
M
M
RC
RCD
RCD
/T
RP
N
M
N
- 1)
- 0.45)
/T
/T
RCD
as follows:
5
4
3
2
1
M
RC
)
= 1.5, this bit is automatically forced to 0 to select 2 MCLK for
M
M
as follows:
)
M
if EDO and N
if EDO and N
if FPM and N
if FPM and N
+ N
+ 1.55)
- 1)
RP
)
RC
RCD
. N
. N
RC
if N
if N
if EDO and N
if EDO and N
if FPM and N
if FPM and N
RP
RP
RP
RP
RCD
RAS#-to-CAS# Delay (t
should be chosen to meet t
= 1 or 2
= 1.5
= 1 or 2
= 1.5
RP
RP
Minimum Random Cycle
= 1 or 2
= 1.5
must be chosen to satisfy the RAS#
ASC
RCD
RC
Width (
Reserved
.
. These bits specify the number
RP
RP
RP
RP
. This bit specifies the number
Epson Research and Development
5
4
3
Hardware Functional Specification
= 1 or 2
= 1.5
2
1
= 1 or 2
= 1.5
t
RC
RC
)
Vancouver Design Center
then choose the larger
RCD
Issue Date: 99/05/18
RC
)
as well as