sed1355 ETC-unknow, sed1355 Datasheet - Page 506

• Manufacturer Part Number: sed1355
• Description: Sed1355 Embedded Ramdac Lcd/crt Controller
• Manufacturer: ETC-unknow

Page 14
4.3 NEC V832 Configuration
SED1355
X23A-G-012-01
Note
The NEC V832 should access the SED1355 in non-burst mode only. This is ensured by
using any one of the CS3 to CS6 lines to control the SED1355 and setting that line to
respond to IO operations using the NEC V832 BCTC register. For example, if line CS5 is
designated to control the SED1355, then bit 5 (CT5) of the BCTC register should be set to
1 (IO cycle).
The NEC V832 data bus should be programmed to use 16 bits as the maximum width for
SED1355 bus transactions. This does not affect the width of other NEC V832 data bus
transactions. Data bus width is set in the NEC V832 DBC register. For example, if line CS4
is designated to control the SED1355, then bit 4 (BW4) of the DBC register should be set
to 1 (16-bit bus width).
Depending on bus clock frequencies, a different number of wait states may be required.
These need to be programmed into the NEC V832 PWC0 and PWC1 registers in the bit
field corresponding to the CSn line chosen for the SED1355. For example, if CS3 controls
the SED1355 and one wait state is required, then bits 14-12 of the NEC V832 PWC0
register (WS3) must be set to 001b (one wait state). If CS6 controls the SED1355 and no
wait state is needed, then bits 11-8 of the NEC V832 PWC1 register (WS6) must be set to
0000b (zero wait state).
The table below shows the recommended wait states depending on the bus clock frequency.
No idle state needs to be added. The NEC V832 PIC0 and PIC1 register bit field
corresponding to the CSn line chosen for the SED1355 must be set to zero. For example, if
CS3 controls the SED1355, then bits 14-12 of the NEC V832 PIC0 register (IS3) must be
set to 000b (no idle state).
The host interface of the SED1355 is slower when disabled. Therefore, while the host
interface is disabled (REG[1Bh] bit 7 = 1), an additional wait state is required to main-
tain the same respective frequency limits.
Table 4-2: NEC
Wait States Maximum Frequency (SDCLKOUT)
0
1
2
V
832 Wait States vs. Bus Clock Frequency
12.5MHz
No limit
37MHz
Interfacing to the NEC V832™ Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 99/05/05