MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 17

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

BURST TERMINATE
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
AUTO REFRESH
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be
precharged prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum
PRECHARGE command as shown in the operations sec-
tion.
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 256Mb
SDRAM requires 8,192 AUTO REFRESH cycles every
64ms (
distributed AUTO REFRESH command every 7.81µs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
The BURST TERMINATE command is used to trun-
AUTO REFRESH is used during normal operation of
The addressing is generated by the internal refresh
t
REF), regardless of width option. Providing a
t
RFC), once every 64ms.
t
RP has been met after the
17
SELF REFRESH
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care” with
the exception of CKE, which must remain LOW.
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
t
nite period beyond that.
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
internal refresh in progress.
commands must be issued every 7.81µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
RAS and may remain in self refresh mode for an indefi-
XSR because time is required for the completion of any
The SELF REFRESH command can be used to retain
Once self refresh mode is engaged, the SDRAM pro-
The procedure for exiting self refresh requires a se-
Upon exiting the self refresh mode, AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16
©2002, Micron Technology, Inc.
SDRAM