MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 51

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11, A12
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
2. x16: A9, A11, and A12 = “Don’t Care”
CLK
CKE
A10
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CKS
t CMS t CMH
MIN
0.8
1.5
2.5
2.5
7.5
0.8
t AS
t AS
t AS
7
ACTIVE
T0
ROW
ROW
BANK
-7E
t CKH
t AH
t AH
t AH
t RCD
MAX
5.4
5.4
t CK
T1
NOP
MIN
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
0.8
1.5
2.5
2.5
7.5
0.8
10
t CMS
t CL
-75
COLUMN m 2
T2
READ
BANK
t CMH
MAX
READ – DQM OPERATION
t CH
5.4
6
CAS Latency
UNITS
T3
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOP
t
LZ
t AC
51
T4
NOP
t OH
D
SYMBOL*
t
t
t
t
t
t
t
t
CKS
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RCD
t HZ
OUT
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t
LZ
MIN
t AC
1.5
0.8
1.5
1
15
1
3
-7E
MAX
256Mb: x4, x8, x16
T6
NOP
5.4
5.4
D
t OH
t AC
OUT
m + 2
MIN
1.5
0.8
1.5
20
1
3
T7
NOP
D
OUT
t OH
-75
t HZ
m + 3
©2002, Micron Technology, Inc.
MAX
SDRAM
5.4
6
T8
NOP
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns