MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 25

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

WRITEs
as shown in Figure 13.
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to the start address
and continue.)
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An ex-
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
WRITE bursts are initiated with a WRITE command,
The starting column and bank addresses are pro-
During WRITE bursts, the first valid data-in ele-
Data for any WRITE burst may be truncated with a
A9, A11, A12: x16
A0-A9, A11: x4
A11, A12: x8
A0-A9: x8
A0-A8: x16
A12: x4
BA0,1
CAS#
RAS#
WE#
A10
CKE
CLK
CS#
WRITE Command
HIGH
Figure 13
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
25
ample is shown in Figure 15. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst. The
256Mb SDRAM uses a pipelined architecture and there-
fore does not require the 2n rule associated with a
prefetch architecture. A WRITE command can be initi-
ated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be per-
formed to a different bank.
COMMAND
ADDRESS
NOTE: Burst length = 2. DQM is LOW.
COMMAND
ADDRESS
CLK
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOTE: DQM is LOW. Each WRITE command
CLK
DQ
WRITE
BANK,
COL n
T0
may be to any bank.
D
WRITE to WRITE
n
IN
WRITE Burst
WRITE
BANK,
COL n
D
T0
Figure 14
Figure 15
n
IN
256Mb: x4, x8, x16
NOP
n + 1
T1
D
IN
n + 1
NOP
T1
D
IN
NOP
T2
WRITE
BANK,
COL b
©2002, Micron Technology, Inc.
T2
D
SDRAM
b
IN
T3
NOP