MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 30

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out ap-
pearing CAS latency later. The PRECHARGE to bank
n will begin after
the READ to bank m is registered. The last valid
WRITE to bank n will be data-in registered one clock
prior to the READ to bank m (Figure 26).
Internal
States
Internal
States
t
WR is met, where
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
WRITE With Auto Precharge Interrupted by a READ
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
Page Active
Page Active
T0
NOP
T0
NOP
t
WR begins when
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
T1
D
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
Figure 27
Figure 26
a + 1
T2
a + 1
T2
D
D
NOP
NOP
IN
IN
30
BANK m,
READ - AP
a + 2
T3
COL d
T3
D
BANK m
NOP
IN
4. Interrupted by a WRITE (with or without auto
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
precharge): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The
PRECHARGE to bank n will begin after
where
registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to
bank m (Figure 27).
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
D
NOP
t
d
IN
WR - BANK n
Interrupt Burst, Write-Back
WRITE with Burst of 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR begins when the WRITE to bank m is
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
T6
T6
256Mb: x4, x8, x16
d + 2
D
NOP
D
NOP
OUT
t RP - BANK n
d
IN
Precharge
DON’T CARE
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
t RP - BANK m
OUT
IN
Write-Back
©2002, Micron Technology, Inc.
SDRAM
t
WR is met,