MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 24

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
Full-page READ bursts can be truncated with the
COMMAND
COMMAND
ADDRESS
ADDRESS
NOTE: DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
COL n
T0
T0
BANK,
COL n
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
Terminating a READ Burst
T2
T2
NOP
NOP
D
OUT
n
Figure 12
T3
T3
24
NOP
NOP
n + 1
D
D
OUT
OUT
n
command, provided that auto precharge was not acti-
vated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
TERMINATE
TERMINATE
T4
BURST
T4
BURST
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 2 cycles
T5
T5
NOP
NOP
n + 3
n + 2
D
D
OUT
OUT
256Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
OUT
DON’T CARE
T7
NOP
©2002, Micron Technology, Inc.
SDRAM