MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 27

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
COMMAND
Fixed-length or full-page WRITE bursts can be trun-
ADDRESS
A0-A9, A11, A12
NOTE: DQMs are LOW.
Terminating a WRITE Burst
BA0, BA1
CLK
DQ
PRECHARGE Command
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
BANK,
WRITE
COL n
D
Figure 19
Figure 20
T0
n
IN
TERMINATE
Bank Selected
BURST
All Banks
ADDRESS
T1
BANK
COMMAND
(ADDRESS)
(DATA)
NEXT
T2
27
PRECHARGE
to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
ter the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When
all banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
POWER-DOWN
dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
power-down. Entering power-down deactivates the in-
put and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the re-
fresh period (64ms) since no refresh operations are
performed in this mode.
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
COMMAND
CKE
CLK
All banks idle
The PRECHARGE command (see Figure 20) is used
Power-down occurs if CKE is registered LOW coinci-
The power-down state is exited by registering a NOP
Enter power-down mode.
t CKS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
Input buffers gated off
Power-Down
t
Figure 21
256Mb: x4, x8, x16
CKS). See Figure 21.
(
(
(
(
)
)
(
)
)
)
(
(
(
(
)
(
)
)
)
)
Exit power-down mode.
> t CKS
NOP
©2002, Micron Technology, Inc.
SDRAM
t
DON’T CARE
RP) af-
ACTIVE
t RCD
t RAS
t RC