MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 55

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
COMMAND
BA0, BA1
DQM/
CKE
A10
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
4. WRITE command not allowed else
DQ
CK
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
ACTIVE
7
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
-7E
t RCD
t RAS
t RC
MAX
t CK
T1
NOP 4
SINGLE WRITE – WITH AUTO PRECHARGE
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
t CL
10
NOP 4
T2
-75
t CH
t
MAX
RAS would be violated.
NOP 4
T3
UNITS
ENABLE AUTO PRECHARGE
ns
ns
ns
ns
ns
ns
ns
ns
ns
t CMS
t DS
COLUMN m 3
BANK
WRITE
T4
D
IN
t CMH
55
t DH
m
t WR
2
SYMBOL*
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1 CLK +
MIN
7ns
1.5
0.8
1.5
37
60
15
15
T6
NOP
-7E
t RP
120,000
MAX
256Mb: x4, x8, x16
1
T7
NOP
1 CLK +
MIN
7.5ns
1.5
0.8
1.5
44
66
20
20
ACTIVE
ROW
BANK
ROW
T8
-75
120,000
©2002, Micron Technology, Inc.
MAX
DON’T CARE
SDRAM
T9
NOP
UNITS
ns
ns
ns
ns
ns
ns
ns
–