MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 40

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11, A12
SYMBOL*
t
t
t
t
t
t
t
DQML, DQMU
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
2. If CS is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care.”
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at
CKE
A10
DQ
CK
MIN
T = 100µs
0.8
1.5
2.5
2.5
7.5
0.8
(
(
(
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7
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Power-up:
V
CLK stable
(
(
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(
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MIN
DD
and
t CKS
t CMS
-7E
T0
NOP
MAX
t CKH
High-Z
t CMH
SINGLE BANK
ALL BANKS
t CK
PRECHARGE
MIN
BANKS
T1
INITIALIZE AND LOAD MODE REGISTER
0.8
1.5
2.5
2.5
7.5
0.8
10
t
ALL
P + 1.
t RP
Precharge
all banks
-75
(
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MAX
Tn + 1
REFRESH
AUTO
t CH
AUTO REFRESH
t RFC
UNITS
ns
ns
ns
ns
ns
ns
ns
NOP
(
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NOP
40
t CL
To + 1
REFRESH
SYMBOL*
t
t
t
t
t
t
AUTO
CKS
CMH
CMS
MRD
RFC
RP
AUTO REFRESH
3
t RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
(
(
(
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(
(
MIN
(
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(
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(
1.5
0.8
1.5
(
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(
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66
15
)
)
)
)
)
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)
2
NOP
-7E
t AS
t AS
MAX
256Mb: x4, x8, x16
LOAD MODE
Tp + 1
2
REGISTER
CODE
CODE
t AH
t AH
Program Mode Register
5
MIN
1.5
0.8
1.5
66
20
t MRD
2
Tp + 2
NOP
-75
©2002, Micron Technology, Inc.
MAX
SDRAM
1, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE
UNDEFINED
UNITS
t
ns
ns
ns
CK
ns
ns