MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 33

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

NOTE (continued):
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
be applied on each positive clock edge during these states.
READs or WRITEs with auto precharge disabled.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
Accessing Mode
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
Register: Starts with registration of a LOAD MODE REGISTER command and ends when
met, the SDRAM will be in the all banks idle state.
met. Once
met, all banks will be in the idle state.
t
MRD is met, the SDRAM will be in the all banks idle state.
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16
t
t
RC is met. Once
RP is met. Once
t
MRD has been
©2002, Micron Technology, Inc.
SDRAM
t
t
RP is
RC is