MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 44

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTES: 1. No maximum time limit for Self Refresh.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11,A12
SYMBOL*
t
t
t
t
t
t
t
DQML, DQMU
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
2.
DQM/
t
XSR requires minimum of two clocks regardless of frequency or timing.
CLK
CKE
A10
DQ
MIN
0.8
1.5
2.5
2.5
7.5
0.8
7
High-Z
Precharge all
t CKS
active banks
t CMS
t
SINGLE BANK
AS
PRECHARGE
ALL BANKS
-7E
BANK(S)
T0
MAX
t CKH
t CMH
t
AH
t CK
MIN
t RP
0.8
1.5
2.5
2.5
7.5
0.8
10
T1
NOP
-75
t CH
Enter self refresh mode
MAX
t CKS
t CL
SELF REFRESH MODE
REFRESH
t
RAS(MAX) applies to non-Self Refresh mode.
AUTO
CLK stable prior to exiting
T2
UNITS
ns
ns
ns
ns
ns
ns
ns
self refresh mode
t RAS(MIN)
(
(
(
(
(
(
(
)
)
(
(
)
(
)
(
)
(
)
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(
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)
)
(
)
(
(
(
(
(
)
(
(
(
)
(
)
(
(
)
(
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(
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(
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(
44
)
)
(
(
)
(
)
)
1
SYMBOL*
t
t
t
t
t
t
CKS
CMH
CMS
RAS
RP
XSR
(Restart refresh time base)
Exit self refresh mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Tn + 1
MIN
1.5
0.8
1.5
37
15
67
t XSR
NOP
-7E
(
(
(
(
(
(
(
(
)
(
)
(
(
)
(
)
(
)
(
)
)
)
)
(
)
)
)
)
)
)
120,000
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
(
)
MAX
)
256Mb: x4, x8, x16
or COMMAND
INHIBIT
To + 1
MIN
1.5
0.8
1.5
44
20
75
-75
To + 2
REFRESH
120,000
©2002, Micron Technology, Inc.
MAX
AUTO
SDRAM
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns