MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 56

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
COMMAND
BA0, BA1
DQM/
2. Requires one clock plus time (7ns or 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 = “Don’t Care”
CLK
CKE
A10
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
ACTIVE
BANK 0
7
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
-7E
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
MAX
t CK
T1
NOP
ENABLE AUTO PRECHARGE
MIN
ALTERNATING BANK WRITE ACCESSES
t CMS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
t CL
t DS
COLUMN m 3
BANK 0
WRITE
T2
D
IN
-75
t CMH
t CH
t DH
m
MAX
t DS
D
IN
T3
NOP
m + 1
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
D
ACTIVE
BANK 1
IN
T4
ROW
ROW
m + 2
56
t DH
t RCD - BANK 1
SYMBOL*
t
t
t
t
t
t
t
t
t
t DS
CMS
DH
DS
RAS
RC
RCD
RP
RRD
WR
D
IN
T5
NOP
m + 3
t DH
t WR - BANK 0
ENABLE AUTO PRECHARGE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Note 2
COLUMN b 3
t DS
MIN
1.5
0.8
1.5
BANK 1
37
60
15
15
14
WRITE
T6
D
IN
t DH
b
-7E
120,000
MAX
256Mb: x4, x8, x16
1
t DS
D
NOP
IN
T7
b + 1
t DH
Note 2
MIN
1.5
0.8
1.5
44
66
20
20
15
t DS
t RP - BANK 0
D
IN
NOP
T8
b + 2
-75
t DH
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
t DS
D
BANK 0
ACTIVE
T9
ROW
IN
ROW
b + 3
t
t
RCD - BANK 0
WR - BANK 1
DON’T CARE
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns