MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 39

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 1.5V with equivalent load:
10.
11. AC operating and I
12. Other input signals are allowed to transition no
13. I
14. Timing actually specified by
15. Timing actually specified by
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
f = 1 MHz, T
Specified values are obtained with minimum cycle
time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range is ensured; (0°C
+70°C for commercial) and
for IT).
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
and V
REFRESH command wake-ups should be repeated
any time the
cation, the clock and CKE must transit between V
and V
manner.
t
the open circuit condition; it is not a reference to
V
t
and V
of 1.5V. If the input transition time is longer than
1ns, then the timing is measured from V
and V
point. Refer to Micron Technical Note TN-48-09.
more than once every two clocks and are otherwise
at valid V
erly initialized.
fied as a reference only at minimum cycle rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
OH
is dependent on output loading and cycle rates.
specifications are tested after the device is prop-
or V
SS
DD
IH
IL
IH
Q must be at same potential.) The two AUTO
= 3.0V using a measurement reference level
Q must be powered up simultaneously. V
(or between V
(MIN) and no longer from the 1.5V mid-
OL
IH
. The last valid data element will meet
or V
A
t
REF refresh requirement is exceeded.
= 25°C; pin under test biased at 1.4V.
Q
IL
levels.
DD
test conditions have V
IL
and V
t
T = 1ns.
SS
t
.
WR plus
t
(-40°C
CKS; clock(s) speci-
IH
DD
50pF
) in a monotonic
, V
DD
t
RP; clock(s)
T
Q = +3.3V;
A
IL
IL
(MAX)
+85°C
T
= 0V
A
DD
IH
SS
39
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times dur-
21.Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and
33. CKE is HIGH during refresh command period
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
specified as a reference only at minimum cycle rate.
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency al-
teration for the test condition.
two clocks.
ing this period.
width
greater than one third of the cycle rate. V
shoot: V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
t
used to reduce the data rate.
budget (
after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge
mode.
t
guaranteed by design.
t
t
ally a nominal value and does not result in a fail
value.
WR, and PRECHARGE commands). CKE may be
AC for -75/-7E at CL = 3 with no load is 4.6ns and is
CK = 7.5ns.
RFC (MIN) else CKE is LOW. The I
IH
overshoot: V
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
t
current will increase or decrease propor-
t
RP) begins 7ns for -7E and 7.5ns for -75
CK = 7.5ns for -75 and -7E.
3ns, and the pulse width cannot be
(MIN) = -2V for a pulse width
IH
256Mb: x4, x8, x16
(MAX) = V
t
CK = 7.5ns; for -7E, CL = 2 and
t
DD
WR.
Q + 2V for a pulse
DD
©2002, Micron Technology, Inc.
6 limit is actu-
SDRAM
3ns.
IL
under-