MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 54

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
BA0, BA1
DQM /
CKE
A10
CLK
DQ
2. 14ns to 15ns is required between <D
3. x16: A8, A9, and A11 = “Don’t Care”
4. PRECHARGE command not allowed else
tWR has been increased to meet minimum tRAS requirement.
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
ACTIVE
7
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
-7E
t RCD
t RAS
t RC
MAX
t CK
T1
NOP
SINGLE WRITE – WITHOUT AUTO PRECHARGE
DISABLE AUTO PRECHARGE
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
t CMS
t CL
t DS
COLUMN m 3
-75
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t WR
MAX
IN
2
m> and the PRECHARGE command, regardless of frequency. With a single write
t
RAS would be violated.
NOP 4
UNITS
T3
ns
ns
ns
ns
ns
ns
ns
ns
ns
54
NOP 4
T4
SYMBOL*
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
SINGLE BANK
PRECHARGE
ALL BANKS
T5
BANK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
1.5
0.8
1.5
37
60
15
15
14
-7E
t RP
120,000
T6
NOP
MAX
256Mb: x4, x8, x16
1
ACTIVE
MIN
BANK
ROW
1.5
0.8
1.5
44
66
20
20
15
T7
-75
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
NOP
T8
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns
ns
ns