MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 19

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

READs
as shown in Figure 5.
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A9, A11, A12: x16
A0–A9, A11:
READ bursts are initiated with a READ command,
The starting column and bank addresses are pro-
During READ bursts, the valid data-out element
A11, A12: x8
A0–A9: x8
A0–A8: x16
A12: x4
BA0,1
CAS#
RAS#
WE#
A10
CKE
CLK
CS#
x4
READ Command
HIGH
Figure 5
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
19
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to the start address and
continue.)
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst that is being truncated. The new
READ command should be issued x cycles before the
clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one.
COMMAND
COMMAND
Upon completion of a burst, assuming no other com-
Data from any READ burst may be truncated with a
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
READ
T0
T0
CAS Latency = 2
CAS Latency
256Mb: x4, x8, x16
NOP
Figure 6
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
©2002, Micron Technology, Inc.
SDRAM
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4