MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 47

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11,A12
SYMBOL*
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
DQML, DQMU
COMMAND
BA0, BA1
DQM /
2. x16: A9, A11, and A12 = “Don’t Care”
3. PRECHARGE command not allowed else
CKE
A10
CLK
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CMS
MIN
t CKS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
t AS
t AS
t AS
7
ACTIVE
ROW
ROW
BANK
T0
t CMH
-7E
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
MAX
5.4
5.4
t CK
T1
NOP
SINGLE READ – WITHOUT AUTO PRECHARGE
DISABLE AUTO PRECHARGE
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
t CMS
t CL
COLUMN m
-75
BANK
T2
READ
t CMH
t CH
MAX
5.4
6
CAS Latency
2
t
RAS would be violated.
UNITS
T3
NOP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t LZ
3
t AC
47
T4
D
NOP
OUT
t OH
t HZ
3
m
SYMBOL*
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RAS
RC
RCD
RP
SINGLE BANKS
PRECHARGE
ALL BANKS
BANK(S)
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
MIN
0.8
1.5
37
60
15
15
1
3
-7E
T6
NOP
120,000
MAX
256Mb: x4, x8, x16
5.4
5.4
1
ACTIVE
ROW
BANK
MIN
T7
ROW
0.8
1.5
44
66
20
20
1
3
-75
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
5.4
6
T8
NOP
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns