MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 42

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11, A12
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
2. x16: A9, A11 and A12 = “Don’t Care”
CKE
A10
CLK
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
COLUMN m
MIN
0.8
1.5
2.5
2.5
7.5
0.8
7
READ
T0
BANK
t CMH
t CKH
t AH
t AH
t AH
-7E
2
MAX
t CMS
5.4
5.4
t CK
T1
NOP
t CMH
MIN
0.8
1.5
2.5
2.5
7.5
0.8
10
t CL
t CKS t CKH
T2
-75
NOP
t LZ
t CH
t AC
MAX
5.4
CLOCK SUSPEND MODE
6
T3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
OUT
m
T4
42
NOP
t OH
t AC
SYMBOL*
t
t
t
t
t
t
t
t
t
CKS
CMH
CMS
DH
DS
HZ (3)
HZ (2)
LZ
OH
D
T5
OUT
NOP
m + 1
t HZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
MIN
1.5
0.8
1.5
0.8
1.5
1
3
T6
NOP
-7E
MAX
256Mb: x4, x8, x16
5.4
5.4
COLUMN e 2
t DS
BANK
WRITE
D
T7
OUT
t DH
e
MIN
1.5
0.8
1.5
0.8
1.5
1
3
-75
T8
©2002, Micron Technology, Inc.
MAX
SDRAM
5.4
6
D
DON’T CARE
UNDEFINED
OUT
T9
NOP
e + 1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns