MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 23

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is either the last of a burst of
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A fixed-length READ burst may be followed by, or
COMMAND
COMMAND
NOTE: DQM is LOW.
ADDRESS
ADDRESS
CLK
CLK
DQ
DQ
BANK a,
BANK a,
COL n
COL n
T0
T0
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
READ to PRECHARGE
T2
T2
NOP
NOP
D
OUT
n
Figure 11
T3
T3
NOP
NOP
23
n + 1
D
D
OUT
OUT
n
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
that part of the row precharge time is hidden during
the access of the last data element(s).
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE
PRECHARGE
In the case of a fixed-length burst being executed to
(a or all)
(a or all)
T4
BANK
BANK
T4
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 2 cycles
T5
T5
NOP
NOP
n + 3
n + 2
D
D
OUT
OUT
t RP
t RP
256Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
OUT
DON’T CARE
BANK a,
BANK a,
ACTIVE
ACTIVE
T7
T7
ROW
ROW
t
RP is met. Note
©2002, Micron Technology, Inc.
SDRAM